XC95108, mgr, Cyfra, Koparka - Ptach,Sierański, 02. Materiały wykorzystane przez dyplomantów, 06. XC95108

//-->.pos {position:absolute; z-index: 0; left: 0px; top: 0px;}RXC95108 In-SystemProgrammable CPLD5DS066 (v4.1) August 21, 2003Product SpecificationFeatures•••••7.5 ns pin-to-pin logic delays on all pinsfCNTto 125 MHz108 macrocells with 2,400 usable gatesUp to 108 user I/O pins5V in-system programmable- Endurance of 10,000 program/erase cycles- Program/erase over full commercial voltage andtemperature rangeEnhanced pin-locking architectureFlexible 36V18 Function Block- 90 product terms drive any or all of 18 macrocellswithin Function Block- Global and product term clocks, output enables,set and reset signalsExtensive IEEE Std 1149.1 boundary-scan (JTAG)supportProgrammable power reduction mode in eachmacrocellSlew rate control on individual outputsUser programmable ground pin capabilityExtended pattern security features for designprotectionHigh-drive 24 mA outputs3.3V or 5V I/O capabilityAdvanced CMOS 5V Fast FLASH™ technologySupports parallel programming of more than oneXC9500 concurrentlyAvailable in 84-pin PLCC, 100-pin PQFP, 100-pinTQFP, and 160-pin PQFP packagesDescriptionThe XC95108 is a high-performance CPLD providingadvanced in-system programming and test capabilities forgeneral purpose logic integration. It is comprised of eight36V18 Function Blocks, providing 2,400 usable gates withpropagation delays of 7.5 ns. SeeFigure 2for the architec-ture overview.Power ManagementPower dissipation can be reduced in the XC95108 by con-figuring macrocells to standard or low-power modes ofoperation. Unused macrocells are turned off to minimizepower dissipation.Operating current for each design can be approximated forspecific operating conditions using the following equation:ICC(mA) = MCHP(1.7) + MCLP(0.9) + MC (0.006 mA/MHz) fWhere:MCHP= Macrocells in high-performance modeMCLP= Macrocells in low-power modeMC = Total number of macrocells usedf = Clock frequency (MHz)Figure 1shows a typical calculation for the XC95108device.300(250)••••••••••••Typical ICC(mA)High P200(180)encerforma(170)oLow P100wer50100DS066_01_110501Clock Frequency (MHz)Figure 1:Typical ICCvs. Frequency for XC95108© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed athttp://www.xilinx.com/legal.htm.All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.DS066 (v4.1) August 21, 2003Product Specificationwww.xilinx.com1-800-255-77781XC95108 In-System Programmable CPLDR3JTAG Port1JTAGControllerIn-System Programming Controller36I/OI/OI/OFast CONNECT II Switch Matrix18FunctionBlock 1Macrocells1 to 18I/O3618FunctionBlock 2Macrocells1 to 18I/OBlocksI/OI/OI/OI/O3I/O/GCK1I/O/GSR2I/O/GTS3618FunctionBlock 3Macrocells1 to 183618FunctionBlock 4Macrocells1 to 183618FunctionBlock 5Macrocells1 to 183618FunctionBlock 6Macrocells1 to 18DS066_02_110101Figure 2:XC95108 ArchitectureFunction block outputs (indicated by the bold line) drive the I/O blocks directly.2www.xilinx.com1-800-255-7778DS066 (v4.1) August 21, 2003Product SpecificationRXC95108 In-System Programmable CPLDAbsolute Maximum RatingsSymbolVCCVINVTSTSTGTJDescriptionSupply voltage relative to GNDInput voltage relative to GNDVoltage applied to 3-state outputStorage temperature (ambient)Junction temperatureValue–0.5 to 7.0–0.5 to VCC+ 0.5–0.5 to VCC+ 0.5–65 to +150+150UnitsVVVoCoCNotes:1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditionsis not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.Recommended Operation ConditionsSymbolVCCINTParameterSupply voltage for internal logicand input buffersSupply voltage for output driversfor 5V operationCommercial TA= 0oC to 70oCIndustrial TA= –40oC to +85oCCommercial TA= 0oC to 70oCIndustrial TA= –40oC to +85oCMin4.754.54.754.53.02.0Max5.255.55.255.53.60.80VCCINT+ 0.5VCCIOVVVVUnitsVVCCIOSupply voltage for output drivers for 3.3V operationVILVIHVOLow-level input voltageHigh-level input voltageOutput voltageQuality and Reliability CharacteristicsSymbolTDRNPEData RetentionProgram/Erase Cycles (Endurance)ParameterMin2010,000Max--UnitsYearsCyclesDC Characteristic Over Recommended Operating ConditionsSymbolVOHVOLIILIIHCINICCParameterOutput high voltage for 5V outputsOutput high voltage for 3.3V outputsOutput low voltage for 5V outputsOutput low voltage for 3.3V outputsInput leakage currentI/O high-Z leakage currentI/O capacitanceOperating supply current(low power mode, active)Test ConditionsIOH= –4.0 mA, VCC= MinIOH= –3.2 mA, VCC= MinIOL= 24 mA, VCC= MinIOL= 10 mA, VCC= MinVCC= MaxVIN= GND or VCCVCC= MaxVIN= GND or VCCVIN= GNDf = 1.0 MHzVI= GND, No loadf = 1.0 MHzMin2.42.4-----Max--0.50.4±10±1010UnitsVVVVµAµApFmA100 (Typical)DS066 (v4.1) August 21, 2003Product Specificationwww.xilinx.com1-800-255-77783XC95108 In-System Programmable CPLDRAC CharacteristicsXC95108-7SymbolTPDTSUTHTCOfCNT(1)ParameterI/O to output validI/O setup time before GCKI/O hold time after GCKGCK to output valid16-bit counter frequencyMin-4.5-125.083.30.54.0-----4.0Max7.5--4.5----8.55.55.59.59.5-XC95108-10Min-6.0-111.166.72.04.0-----4.5Max10.0--6.0----10.06.06.010.010.0-XC95108-15Min-8.0-95.255.64.04.0-----5.5Max15.0--8.0----12.011.011.014.014.0-XC95108-20Min-10.0-83.350.04.06.0-----5.5Max20.0--10.0----16.016.016.018.018.0-UnitsnsnsnsnsMHzMHznsnsnsnsnsnsnsnsfSYSTEM(2)Multiple FB internal operatingfrequencyTPSUTPHTPCOTOETODTPOETPODTWLHI/O setup time before p-term clockinputI/O hold time after p-term clock inputP-term clock output validGTS to output validGTS to output disableProduct term OE to output enabledProduct term OE to output disabledGCK pulse width (High or Low)Notes:1. fCNTis the fastest 16-bit counter frequency available, using the local feedback when applicable.fCNTis also the Export Control Maximum flip-flop toggle rate, fTOG.2. fSYSTEMis the internal operating frequency for general purpose system designs spanning multiple FBs.VTESTR1Device OutputR2CLOutput TypeVCCIO5.0V3.3VVTEST5.0V3.3VR1160Ω260ΩR2120Ω360ΩCL35 pF35 pFDS067_03_110101Figure 3:AC Load Circuit4www.xilinx.com1-800-255-7778DS066 (v4.1) August 21, 2003Product SpecificationRXC95108 In-System Programmable CPLDInternal Timing ParametersXC95108-7SymbolBuffer DelaysTINTGCKTGSRTGTSTOUTTENInput buffer delayGCK buffer delayGSR buffer delayGTS buffer delayOutput buffer delayOutput buffer enable/disable delay------2.51.54.55.52.5------3.52.56.06.03.0------4.53.07.511.04.5------6.53.09.516.06.5nsnsnsnsnsnsParameterMinMaxXC95108-10MinMaxXC95108-15MinMaxXC95108-20MinMaxUnitsProduct Term Control DelaysTPTCKTPTSRTPTTSProduct term clock delayProduct term set/reset delayProduct term 3-state delay---3.02.04.5---3.02.53.5---2.53.05.0---2.53.05.0nsnsnsInternal Register and Combinatorial DelaysTPDITSUITHITCOITAOITRAITLOGICombinatorial logic propagation delayRegister setup timeRegister hold timeRegister clock to output valid timeRegister async. S/R to output delayRegister async. S/R recover before clockInternal logic delay-1.53.0--7.5--0.5--0.56.5-2.010.0-2.53.5--10.0--1.0--0.57.0-2.511.0-3.54.5--10.0--3.0--0.58.0-3.011.5-3.56.5--10.0--4.0--0.58.0-3.011.5nsnsnsnsnsnsnsnsTLOGILPInternal low power logic delayFeedback DelaysTFTLFFast CONNECT II feedback delayFunction block local feedback delay--8.04.0--9.53.5--11.03.5--13.05.0nsnsTime AddersTPTA(1)Incremental product term allocator delayTSLEWSlew-rate limited delay--1.04.0--1.04.5--1.05.0--1.55.5nsnsNotes:1. TPTAis multiplied by the span of the function as defined in the XC9500 family data sheet.DS066 (v4.1) August 21, 2003Product Specificationwww.xilinx.com1-800-255-77785

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