A
PPLICATION
N
OTES
AVAILABLE
AN4 • AN12 • AN22 • AN26 • AN32
128 Bit
X24C00
16 x 8 Bit
Serial E
2
PROM
FEATURES
•
2.7V to 5.5V Power Supply
•
128 Bit Serial E
2
PROM
•
Low Power CMOS
—Active Current Less Than 3mA
—Standby Current Less Than 50
DESCRIPTION
The X24C00 is a CMOS 128 bit serial E
2
PROM, inter-
nally organized as 16 x 8. The X24C00 features a serial
interface and software protocol allowing operation on a
simple two wire bus.
•
Internally Organized 16 x 8
•
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
•
Byte Mode Write
•
Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
•
Push/Pull Output
•
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
•
Available Packages
—8-Lead MSOP
—8-Lead PDIP
—8-Lead SOIC
m
A
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
The X24C00 is fabricated with Xicor’s Advanced CMOS
Floating Gate technology.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
MSOP/DIP/SOIC
SCL
CONTROL
LOGIC
COMMAND/ADDRESS
REGISTER
NC
NC
NC
V
SS
1
2
3
4
8
7
6
5
V
CC
NC
SCL
SDA
X24C00
INPUT/
OUTPUT
BUFFER
SDA
SHIFT REGISTER
3836 FHD F02.1
MEMORY ARRAY
3836 FHD F01
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
1
Characteristics subject to change without notice
3836-1.5 6/10/96 T2/C1/D0 NS
X24C00
PIN DESCRIPTIONS
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is a push/pull output and does not
require the use of a pull-up resistor.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C00 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
PIN NAMES
Symbol
Description
A start may be issued to terminate the input of a control
word or the input of data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start
cannot be generated while the part is outputting data.
Starts are also inhibited while a write is in progress.
NC
No Connect
V
SS
Ground
V
CC
Supply Voltage
SDA
Serial Data
SCL
Serial Clock
Stop Condition
The stop condition is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is used to reset
the device during a command or data input sequence
and will leave the device in the standby mode. As with
starts, stops are inhibited when outputting data and
while a write is in progress.
3836 PGM T01
DEVICE OPERATION
The X24C00 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. There-
fore, the X24C00 will be considered a slave in all
applications.
Write Operation
The byte write operation is initiated with a start condition.
The start condition is followed by an eight bit control byte
which consists of a two bit write command (0,1), four
address bits, and two “don’t care” bits (Figure 3).
2
X24C00
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
3836 FHD F03
Figure 2. Definition of Start and Stop Conditions
SCL
SDA
START CONDITION
STOP CONDITION
3836 FHD F04
Figure 3. Control Byte
START
C1 C2 A3 A2 A1 A0 XX XX
3836 FHD F05
3
X24C00
After receipt of the control byte, the X24C00 will enter
the write mode and await the data to be written. This data
is shifted into the device on the next eight SCL clocks.
Once eight clocks have been received, the data in the
shift register will be written into the memory array. While
the write is in progress the X24C00 will not respond to
any inputs. At any time prior to clocking in the last data
bit, a stop command or a new start command will
terminate the operation. If a start command is given, the
X24C00 will reset all counters and will prepare to clock
in the next control byte. If a stop command is given, the
X24C00 will reset all counters and await the next start
command.
Read Operation
The byte read operation is initiated with a start condition.
The start condition is followed by an eight-bit control byte
which consists of a two-bit read command (1,0), four
address bits, and two “don’t care” bits. After receipt of
the control byte the X24C00 will enter the read mode and
transfer data into the shift register from the array. This
data is shifted out of the device on the next eight SCL
clocks. At the end of the read, all counters are reset and
the X24C00 will enter the standby mode. As with a write,
the read operation can be interrupted by a start or stop
condition while the command or address is being clocked
in. While clocking data out, starts or stops cannot be
generated.
At the end of the write the X24C00 will automatically
reset all counters and enter the standby mode.
(Figure 4).
During the second don’t care clock cycle, starts and
stops are ignored. The master must free the bus prior to
the end of this clock cycle to allow the X24C00 to begin
outputting data (Figures 5 and 6).
Figure 4. Write Sequence
START
0
1 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0
3836 FHD F06
Figure 5. Read Sequence
START
1
0 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0
3836 FHD F07
Figure 6. Read Cycle Timing
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
SCK
6
7
8
1
Must be
steady
Will be
steady
SDA IN
A0
XX
XX
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
SDA OUT
D7
D6
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
3836 FHD F08
4
X24C00
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X24C00 ...................................... –65
°
C to +135
°
C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Storage Temperature ....................... –65
°
C to +150
°
C
Voltage on any Pin with
Respect to V
SS
............................................
–1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300
°
C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
0
°
C
+70
°
C
X24C00
5V
±
10%
Industrial
–40
°
C
+85
°
C
X24C00-3
3V to 5.5V
Military
–55
°
C
C
3836 PGM T02.1
°
X24C00-2.7
2.7V to 5.5V
3836 PGM T03.1
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
l
CC1
V
CC
Supply Current Read
1
mA
SCL = VCC x 0.1/VCC x 0.9
I
CC2
V
CC
Supply Current Write
3
Levels @ 1MHz, SDA = Open
I
SB1
V
CC
Standby Current
100
m
A
SCL = SDA = V
CC
V
CC
= 5V
±
10%
I
SB2
V
CC
Standby Current
50
m
A
SCL = SDA = V
CC
V
CC
= 2.7V
I
LI
Input Leakage Current
10
m
A
V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current
10
m
A
V
OUT
= V
SS
to V
CC
V
lL
(1)
Input LOW Voltage
–1
V
CC
x 0.3
V
V
IH
(1)
Input HIGH Voltage
V
CC
x 0.7 V
CC
+ 0.5
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 2.1mA
V
OH
Output HIGH Voltage
V
CC
– 0.8
V
I
OH
= 1mA
3841 PGM T04.3
CAPACITANCE
T
A
= +25
°
C, f = 1MHz, V
CC
= 5V
Symbol
Parameter
Max.
Units
Test Conditions
C
I/O
(2)
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
(2)
Input Capacitance (SCL)
6
pF
V
IN
= 0V
3836 PGM T05.1
Notes:
(1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
5
+125